The generation of continuous signals, for example clock signals, having a predetermined phase shift with respect to a reference signal are used in many different applications. For example, shifting a clock signal by a constant phase, for example by 90°, is using during sampling of received data in a receiver component of a communication device to sample the received data in the center of a data eye. Furthermore, in so-called polyphase filters a phase shift of 90° is applied to signals irrespective of the frequency. Moreover, generating signals having a predetermined phase shift with respect to a reference signal is also used for the time-wise calibration of a plurality of signals or for the time-wise matching of signal sources. Devices for generating an output signal having a predetermined phase shift with respect to a reference signal can also be designed for using so-called early-late phase detectors, for example so-called Hogge-detectors.
As regards the above-mentioned applications, several solutions are known from the prior art. Conventionally, delay elements are used for generating an output signal having a predetermined phase shift with respect to an input signal. These delay elements may comprise a plurality of gates connected in series, which is the simplest embodiment of such a delay device.
FIG. 10 shows a device or circuit arrangement which is often used for shifting a clock signal by 90°. According to FIG. 10, chip-internal passive filters comprising an RC network with resistors and capacitances. This passive RC network is a frequency selective network for generating an output signal OUT2 having a phase shift of ±90° with respect to an input signal IN. In addition, the circuit arrangement of FIG. 10 generates an output signal OUT1 having no phase shift with respect to the input signal IN. In order to obtain an output signal which is the inverted version of the input signal IN, the same RC network would have to be used one more time to shift the output signal OUT2 by further 90°. The problem of the solution shown in FIG. 10 is that the required space is relatively high and the electric components have tolerances which are problematic in many applications, especially in applications which require a very precise phase shift of the output signal with respect to the input signal.
Other conventional devices for generating an output signal having a predetermined phase shift with respect to an input signal are based on the principle of a so-called delay locked loop (DLL).
FIG. 11 shows an example for such a conventional DLL-based device which, in particular, can be used for the time-wise calibration of a plurality of signals. According to FIG. 11, the DLL comprises a plurality of identical voltage controlled delay elements 41 connected in series and a phase detector 42. The input signal of the first delay element 41 and of the phase detector 42 is the output signal of a demultiplexer 40 which receives a plurality of input signals IN1–IN3 which are to be calibrated. Furthermore, the demultiplexer 40 is controlled by a selection signal SEL for selecting one of the input signals IN1–IN3 as an input signal for the DLL. The phase detector 42 compares the phase of the output signal of the last delay element with the phase of the input signal of the DLL, that is to say the output signal of the demultiplexer 40, which serves as a reference signal for the DLL. The output signals A–C of individual delay element 41 are supplied to a multiplexer 43 which is also controlled by the selection signal SEL. Depending on the phase comparison of the phase detector 42 the delay time of the individual delay elements 41 is controlled by the phase detector 42. The time shift between signals A and B is for example T1, while the time shift between signals B and C is for example T2≠T1. After the calibration of the input signals IN1–IN3 has been completed, for each input signal IN1–IN3 the appropriate delay element 41 of the chain of delay elements is determined, whose output signal is supplied to the multiplexer 43. One problem of the circuit arrangement shown in FIG. 11 is the relatively large number of circuit components and the required space. Even more important, however, is that the time-wise calibration can only be as precise as the delay time of one individual delay element 41, which is often insufficient for applications requiring a very precise calibration of a plurality of input signals.
In various applications phase detectors are used to detect a phase error between a reference signal and an output signal. For example, it is the function of a clock and data recovery circuit of a communication device to create a properly aligned clock to an incoming data pattern, and to retime the input data according to that clock. This is accomplished by using a PLL, and a phase error signal is produced and used to properly set the phase and frequency of a voltage controlled oscillator (VCO) through closed loop feedback. The generation of the phase error signal is generally performed by phase detector designs, which are classified as either linear and bang-bang approaches. Linear phase detectors, for which the Hogge-detector is a common implementation, create a continuous error signal that leads to linear behaviour in the tracking characteristics of the PLL, while bang-bang detectors generate a quantized phase error signal, which leads to non-linear tracking characteristics.
An example for a conventional Hogge phase detector design is shown in FIG. 12. The circuit of FIG. 12 comprises a first register or flip-flop 50 connected in series with a second register or flip-flop 51 acting as a latch. Both flip-flops 50, 51 are master-slave flip-flops. The input data is supplied to the first flip-flop 50. The data signal DATA is combined with the output signal of the first flip-flop 50 by a first XOR gate 53 to create an UP phase error signal, while the output signal of the first flip-flop 50 and the output signal of the second flip-flop 51 are combined by a second XOR gate 54 to create a DOWN phase error signal. Both flip-flops 50, 51 are inversely operated by a clock signal CLK using an inverter 52. The output signal of the second flip-flop 51 corresponds to the retimed data signal DATA′, and the phase error signals UP/DOWN indicate whether the clock signal CLK lags or leads the data signal DATA acting as a reference signal so as to be able to properly align the phase shift of the clock signal CLK with respect to the incoming data signal DATA.
The Hogge phase detector shown in FIG. 12 is an easy to implement phase detector design, but it works with fixed, that is non-variable, sampling times. Consequently, the sampling times cannot be adapted to the respective task. In addition, the Hogge phase detector design requires a critical alignment of the run time of the first flip-flop 50 shown in FIG. 12.